The objective of this research is to develop performance simulation capabilities to allow system level analysis and prediction of performance of the next generation complex PetaFlop machines that include multiple levels of memory hierarchy and interconnects. The performance simulator developed in this project is used to test parallel data structures and algorithms implemented in programming environments used in these machines, as well as frameworks to enable the development of applications for these machine classes. A number of important applications are used to test and validate the CS technology advances.
Project Publications:
A list of all publicationsi produced in this project can be found in
this document
Software Products:
Information about the emulation software, and instructions
for downloading, are available
here
Enhancements to the Charm++ distribution, including all the
simulations tools that we developed, are available
here
Related Links:
Materials from all Charm++ workshops, including archivals
of tutorial presentations, are available at
this site