Live Webcast 15th Annual Charm++ Workshop

Power and energy efficiency is one of the major challenges to achieve exascale computing in the next several years. While chips operating near threshold voltage have been studied to be highly energy-efficient, Near Threshold Voltage (NTV) operation leads to heterogeneity across cores within the microprocessor chip. In this work, we study chips with NTV operation and discuss programming systems, and performance modeling in the presence of heterogeneity. We propose an integer linear programming based approach for selecting optimal configuration of a chip that minimizes its energy consumption. We obtain an average of 26% and 10.7% savings in energy consumption of the chip for two HPC mini-applications - miniMD and Jacobi, respectively. These energy savings are significantly more than the savings by sub-optimal configurations obtained from heuristics.