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A Pattern Language for Topology Aware Mapping
Workshop on Parallel Programming Patterns (ParaPLoP) 2009
Publication Type: Paper
Repository URL: 200904_TopoPatterns
Abstract
Obtaining the best performance from a parallel program involves four important steps: 1. Choice of the appropriate grainsize; 2. Balancing computational and communication load across processors; 3. Optimizing communication by minimizing inter-processor communication and overlap of communication with computation; and 4. Minimizing communication traffic on the network by topology aware mapping. In this paper, we will present a pattern language for the fourth step where we deploy topology aware mapping to minimize communication traffic on the network and optimize performance. Bandwidth occupancy of network links by different messages at the same time leads to contention which increases message latencies. Topology aware mapping of communicating tasks on the physical processors can avoid this and improve application performance significantly.
TextRef
Abhinav Bhatele, Laxmikant V. Kale, Nicholas Chen and Ralph E. Johnson, A Pattern Language for Topology Aware Mapping, Workshop on Parallel Programming Patterns (ParaPLOP 2009), 2009
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