Temperature Aware Load Balancing for Parallel Applications: Preliminary Work
Workshop on High-Peformance Power Aware Computing at IPDPS (HPPAC) 2011
Publication Type: Paper
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Increasing number of cores and clock speeds on a smaller chip area implies more heat dissipation and an ever increasing heat density. This increased heat, in turn, leads to higher cooling cost and occurrence of hot spots. Effective use of dynamic voltage and frequency scaling (DVFS) can help us alleviate this problem. But there is an associated execution time penalty which can get amplified in parallel applications. In high performance computing, applications are typically tightly coupled and even a single overloaded core can adversely affect the execution time of the entire application. This makes load balancing of utmost value. In this paper, we outline a temperature aware load balancing scheme, which uses DVFS to keep core temperatures below a user-defined threshold with minimum timing penalty. While doing so, it also reduces the possibility of hot spots. We apply our scheme to three parallel applications with different energy consumption profiles. Results from our technique show that we save up to 14% in execution time and 12% in machine energy consumption as compared to frequency scaling without using load balancing. We are also able to bound the average temperature of all the cores and reduce the temperature deviation amongst the cores by a factor of 3.
Osman Sarood and Abishek Gupta and Laxmikant V. Kale, "Temperature Aware Load Balancing for Parallel Applications: Preliminary Work", Parallel Programming Laboratory, Department of Computer Science, University of Illinois at Urbana-Champaign, Proceedings of High Performance Power Aware Computing (HPPAC) in IEEE International Parallel and Distributed Processing Symposium 2011, May 2011.
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