Scheduling for HPC Systems with Process Variation Heterogeneity
PPL Technical Report 2014
Publication Type: Paper
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Variation in the CMOS manufacturing processes cause the transistors on each chip to differ, which results in many-core chips being inherently heterogeneous. For example, frequency and power consumption profiles of cores can span a wide range. This makes optimal scheduling of applications under a power budget computationally difficult, because of the combinatorially large number of choices available. To facilitate this, we model the performance and power consumption of HPC applications on such heterogeneous chips. Based on our models, we propose a scheduling framework using integer linear programming (ILP), which enables efficient scheduling with various power consumption and performance constraints. Using this framework, an HPC runtime system can decide how many and which cores of a chip to use depending on the application, the properties of the chip, and the imposed constraints. Our results show that our framework finds configurations that are up to 2.5 times faster than the ones obtained from simple heuristics. We also propose various research directions for this problem based on our framework.
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