Energy-optimal Configuration Selection for Manycore Chips with Variation
International Journal for High Performance Computing Applications (IJHPCA) 2016
Publication Type: Paper
Operating chips at high energy-efficiency is one of the major challenges for modern large scale supercomputers. Low voltage operation of transistors increases the energy efficiency but leads to frequency and power variation across cores on the same chip. Finding energy-optimal configurations for such chips is a hard problem. In this work, we study how integer linear programming techniques can be used to obtain energy efficient configurations of chips that have heterogeneous cores. Our proposed methodologies give optimal configurations as compared to competent but sub-optimal heuristics while having negligible timing overhead. The proposed ParSearch method gives up to 13.2% and 7% savings in energy while causing only 2% increase in execution time of two HPC applications - miniMD and Jacobi, respectively. Our results show that integer linear programming can be a very powerful online method to obtain energy-optimal configurations.