Implementing a Parallel Prolog Interpreter on Multiprocessors
International Parallel Processing Symposium (IPPS) 1991
Publication Type: Paper
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Abstract
We describe the implementation of the Reduce-OR process model for the parallel execution of logic programs in an interpreter for parallel Prolog. The interpreter supports full OR and independent AND parallelism in logic programs on both shared and nonshared memory machines. The process model has been implemented on top of a run time support system called the Chare Kernel. The Chare Kernel makes it possible to keep the interpreter machine independent by assuming responsibility for dynamic load balancing, scheduling, memory and task queue management. The interpreter currently runs on the Sequent Balance, the Alliant FX/8, the Encore Multimax and the Intel iPSC/2 hypercube. This implementation provides valuable information for the design and development of a compiler for the Reduce-OR process model.
TextRef
L.V. Kale and B. Ramkumar, "Implementing a Parallel Prolog Interpreter on Multiprocessors", 5th International Parallel Processing Symposium, Anaheim, CA, April 1991, pp. 543-548.
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