Program Optimizing and Tuning Seminar Series

Topology Aware Mapping for Performance Optimization of Science Applications

Wednesday, October 8th, 2008

Siebel Center, Room 4405

Speaker: Abhinav S Bhatele Parallel Programming Lab, UIUC

Abstract:

The emergence of large machines with 3D mesh/torus interconnects and significant dependence of message latencies on hops (links) traversed by messages have led to the re-emergence of topology aware mapping as a technique for optimizing communication and improving performance. In this talk, I will motivate why it is important to pay attention to topology-aware mapping. I will then discuss the application of this technique to two production codes, NAMD and OpenAtom and performance improvements obtained as a result. I will also mention some other CSE applications which can benefit from mapping and future work on a general automatic framework which can do mapping for applications automatically. This will relieve the application developers of the burden of manually defining a mapping.

Speaker's Biography

Abhinav Bhatele received a B. Tech. degree in Computer Science from I.I.T. Kanpur in 2005 and a M. S. degree in Computer Science from the University of Illinois in 2007. He is a doctoral student with Prof. Laxmikant V. Kale in the Parallel Programming Laboratory. His research interests include topology aware mapping, scalable load balancing and performance analysis and tuning of CSE applications.